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19-1565; Rev 0; 10/99
+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
General Description
The MAX5102 parallel-input, voltage-output, dual 8-bit digital-to-analog converter (DAC) operates from a single +2.7V to +5.5V supply and comes in a space-saving 16-pin TSSOP package. Internal precision buffers swing Rail-to-Rail (R) , and the reference input range includes both ground and the positive rail. Both DACs share a common reference input. The MAX5102 has separate input latches for each of its DACs. Data is transferred to the input latches from a common 8-bit input port. The DACs are individually selected through address input A0 and are updated by bringing WR low. The MAX5102 features a shutdown mode that reduces current to 1nA, as well as a power-on reset mode that resets all registers to code 00 hex on power-up.
PART MAX5102AEUE MAX5102BEUE
Features
o +2.7V to +5.5V Single-Supply Operation o Ultra-Low Supply Current 0.2mA while Operating 1nA in Shutdown Mode o Ultra-Small 16-Pin TSSOP Package o Ground to VDD Reference Input Range o Output Buffer Amplifiers Swing Rail-to-Rail o Power-On Reset Sets All Registers to Zero
MAX5102
Ordering Information
TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 TSSOP INL (LSB) 1 2
Applications
Digital Gain and Offset Adjustment Programmable Attenuators Portable Instruments Power-Amp Bias Control
Functional Diagram
TOP VIEW
VDD 1 REF 2 SHDN 3
INPUT LATCH B
Pin Configuration
INPUT LATCH A D0-D7
DAC A
OUTA
16 OUTA 15 OUTB 14 GND
WR 4
DAC B OUTB
MAX5102
13 A0 12 D0 11 D1 10 D2 9 D3
D7 5 D6 6 D5 7
A0
CONTROL LOGIC
D4 8
MAX5102
TSSOP
WR REF SHDN
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. ________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5102
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V D_, A0, WR, SHDN to GND ......................................-0.3V to +6V REF to GND ................................................-0.3V to (VDD + 0.3V) OUT_ to GND ...........................................................-0.3V to VDD Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 5.7mW/C above +70C) .......457mW Operating Temperature Range MAX5102_EUE ..............................................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VREF = +2.7V to +5.5V, GND = 0V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF = +3V and TA = +25C.) PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Zero-Code Error Zero-Code-Error Supply Rejection Zero-Code Temperature Coefficient Gain Error (Note 2) Gain-Error Temperature Coefficient INL DNL ZCE MAX5102A MAX5102B Guaranteed monotonic Code = 00 hex Code = 00 hex, VDD = 2.7V to 5.5V Code = 00 hex Code = F0 hex Code = F0 hex VDD = 2.7V to 3.6V, VREF = 2.5V VDD = 4.5V to 5.5V, VREF = 4.096V 0 320 460 15 RL = VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V VIN = VDD or GND 10 0 2 3 0.8 1.0 VREF 0.001 1 LSB 1 10 1 SYMBOL CONDITIONS MIN TYP MAX 8 1 2 1 20 10 UNITS Bits LSB LSB mV mV V/C % LSB/C
Power-Supply Rejection
Code = FF hex Code = FF hex
REFERENCE INPUT Input Voltage Range Input Resistance Input Capacitance DAC OUTPUTS Output Voltage Range DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance 2 VIH VIL IIN CIN VDD 600 V k pF V
V V A pF
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+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VREF = +2.7V to +5.5V, GND = 0V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF = +3V and TA = +25C.) PARAMETER DYNAMIC PERFORMANCE Output Voltage Slew Rate Output Settling Time (Note 3) Channel-to-Channel Isolation (Note 4) Digital Feedthrough (Note 5) Digital-to-Analog Glitch Impulse From code 00 to code F0 hex To 1/2LSB, from code 00 to code F0 hex Code 00 to code FF hex Code 00 to code FF hex Code 80 hex to code 7F hex REF = 2.5Vp-p at 1kHz, VREF(DC) = 1.5V, VDD = 3V, code FF hex REF = 2.5Vp-p at 10kHz, VREF(DC) = 1.5V, VDD = 3V, code FF hex REF = 0.5Vp-p, VREF(DC) = 1.5V, VDD = 3V, -3dB bandwidth tSDR tSDN VDD IDD To 1/2LSB of final value of VOUT IDD < 5A 2.7 190 0.001 tAS tAH tDS tDH tWR 5 0 25 0 20 0.6 6 500 0.5 90 70 dB 60 650 60 13 20 5.5 360 1 kHz VRMS s s V A A ns ns ns ns ns V/s s nVs nVs nVs SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5102
Signal-to-Noise plus Distortion Ratio
SINAD
Multiplying Bandwidth Wideband Amplifier Noise Shutdown Recovery Time Time to Shutdown POWER SUPPLIES Power-Supply Voltage Supply Current (Note 6) Shutdown Current DIGITAL TIMING (Figure 1) (Note 7) Address to WR Setup Address to WR Hold Data to WR Setup Data to WR Hold WR Pulse Width
Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded. Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VREF]. Where VF0,meas is the DAC output voltage with input code F0 hex, and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VREF * 240 / 256). Note 3: Output settling time is measured from the 50% point of the falling edge of WR to 1/2LSB of VOUT's final value. Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any other DAC output. The measured channel has a fixed code of 80 hex. Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight data inputs with WR at VDD. Note 6: RL = , digital inputs at GND or VDD. Note 7: Timing measurement reference level is (VIH + VIL) / 2.
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3
+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5102
ADDRESS tAS WR ADDRESS VALID tWR tAH-
tDSDATA DATA VALID
tDH-
Figure 1. Timing Diagram
Typical Operating Characteristics
(VDD = VREF = +3V, RL = 10k, CL = 100pF, code = FF hex, TA = +25C, unless otherwise noted.)
DAC ZERO-CODE OUTPUT VOLTAGE vs. SINK CURRENT
MAX5102 toc01
DAC FULL-SCALE OUTPUT VOLTAGE vs. SOURCE CURRENT
MAX5102 toc02
SUPPLY CURRENT vs. TEMPERATURE
190 180 SUPPLY CURRENT (A) 170 160 150 140 130 120 110 VDD = 3.0V -40 -20 0 20 40 60 80 100 VDD = 5V; CODE = 00 VDD = 3V; CODE = 00 VDD = 3V; CODE = F0 HEX 1 DAC AT CODE 00 OR F0 1 DAC AT CODE 00 (RL = ) VDD = 5V; CODE = F0 HEX
MAX5102 toc03
1.2 1.0 0.8 VOUT (V)
6 5 4 VOUT (V) 3 2 1 0 VDD = VREF = 3V VDD = VREF = 5V
200
VDD = VREF = 3V
0.6 0.4 0.2 0 0 2 4 6 8 10 SINK CURRENT (mA) VDD = VREF = 5V
100 0 2 4 6 8 10 SOURCE CURRENT (mA)
TEMPERATURE (C)
SUPPLY CURRENT vs. REFERENCE VOLTAGE
MAX5102 toc04
SUPPLY CURRENT vs. REFERENCE VOLTAGE
MAX5102 toc05
180 160 SUPPLY CURRENT (A) 140 120 100 80 60 40 20 0 0
1 DAC AT CODE 00 OR F0 1 DAC AT CODE 00 (RL = ) CODE = F0 HEX CODE = 00 HEX
180 160 SUPPLY CURRENT (A) 140 120 100 80 60 40 VDD = 5.0V 1 DAC AT CODE 00 OR F0 1 DAC AT CODE 00. (RL = ) 0 CODE = 00 HEX CODE = F0 HEX
-10 -20 THD + NOISE (dB) -30 -40 -50 -60 -70 -80
DAC CODE = FF HEX VREF = SINE WAVE CENTERED AT 1.5V 80kHz FILTER
20kHz REF SIGNAL 10kHz REF SIGNAL
VDD = 3.0V 0.5 1.0 1.5 2.0 2.5 3.0
20 0
1kHz REF SIGNAL -90 0 0.5 1.0 1.5 2.0 2.5 REFERENCE AMPLITUDE (Vp-p)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5. 5.0 REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
4
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MAX5102 toc06
200
200
0
TOTAL HARMONIC DISTORTION PLUS NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE
+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
Typical Operating Characteristics (continued)
(VDD = VREF = +3V, RL = 10k, CL = 100pF, code = FF hex, TA = +25C, unless otherwise noted.)
REFERENCE INPUT FREQUENCY RESPONSE
MAX5100 toc08
MAX5102
MAX5102 toc07
0 -10 -20 THD + NOISE (dB) -30 -40 -50 -60 -70 -80 1
OUTPUT AMPLITUDE (dB)
DAC CODE = FF HEX VREF = SINE WAVE CENTERED AT 1.5V 1kHz FREQUENCY 500kHz FILTER
0 -10 -20 -30 -40 -50 -60 -70
DAC CODE FROM 80 TO 7F HEX
1
REF = 0.5Vp-p
REF = 1Vp-p
2 CODE = FF HEX REF IS IVp-p SIGNAL VREF = 1.5V 0.01 0.1 1 10 2s/div CH1 = WR, 1V/div, CH2 = VOUTA, 50mV/div, AC-COUPLED
REF = 2Vp-p
-80 -90
10 FREQUENCY (kHz)
100
FREQUENCY (MHz)
WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE)
MAX55102 toc10
DIGITAL FEEDTHROUGH GLITCH IMPULSE (0 TO 1 DIGITAL TRANSITION)
MAX55102 toc11
DIGITAL FEEDTHROUGH GLITCH IMPULSE (1 TO 0 DIGITAL TRANSITION)
1 TO 0 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH)
MAX55102 toc12
DAC CODE FROM 7F TO 80 HEX
0 TO 1 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH)
1 2
1 2
1 2
1s/div CH1 = WR, 1V/div, CH2 = VOUTA, 50mV/div, AC-COUPLED
20ns/div CH1 = D7, 2V/div, CH2 = VOUTA, 1mV/div
20ns/div CH1 = D7, 2V/div, CH2 = VOUTA, 1mV/div
POSITIVE SETTLING TIME
MAX55102 toc13
NEGATIVE SETTLING TIME
MAX55102 toc14
INTEGRAL AND DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE
0.4 0.3 0.2 INL/DNL (LSB) DNL RL =
MAX5102 toc15
0.5
DAC CODE FROM 10 TO F0 HEX
DAC CODE FROM F0 TO 10 HEX
1
1
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
2
2
INL
1s/div CH1 = WR = 2V/div, CH2 = VOUTA = 2V/div
1s/div CH1 = WR, 2V/div, CH2 = VOUTA, 2V/div
0
32
64
96
128 160 192 224 256
DIGITAL CODE
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5
MAX55102 toc09
TOTAL HARMONIC DISTORTION PLUS NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY
WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE)
10
+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5102
Pin Description
PIN 1 2 3 4 5-12 13 14 15 16 NAME VDD REF SHDN WR D7-D0 A0 GND OUTB OUTA FUNCTION Positive Supply Voltage. Bypass VDD to GND using a 0.1F capacitor. Reference Voltage Input Shutdown. Connect SHDN to GND for normal operation. Write Input (active low). Use WR to load data into the DAC input latch selected by A0. Data Inputs DAC Address Select Bit Ground DAC B Voltage Output DAC A Voltage Output
Detailed Description
Digital-to-Analog Section
The MAX5102 uses a matrix decoding architecture for the DACs. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor network converts the 8-bit digital input into an equivalent analog output voltage in proportion to the applied reference voltage input. The resistor string presents a codeindependent input impedance to the reference and guarantees a monotonic output. These devices can be used in multiplying applications. Their voltages are buffered by rail-to-rail op amps connected in a follower configuration to provide a rail-to-rail output (see Functional Diagram).
Reference Input
The MAX5102 provides a code-independent input impedance on the REF input. Input impedance is typically 460k in parallel with 15pF, and the reference input voltage range is 0 to VDD. The reference input accepts positive DC signals, as well as AC signals with peak values between 0 and VDD. The voltage at REF sets the full-scale output voltage for the DAC. The output voltage (VOUT) for any DAC is represented by a digitally programmable voltage source as follows: VOUT = (NB * VREF) / 256 where NB is the numeric value of the DAC binary input code.
Digital Inputs and Interface Logic
In the MAX5102, address line A0 selects the DAC that receives data from D0-D7, as shown in Table 1. When WR is low, the addressed DAC's input latch is transparent. Data is latched when WR is high. The DAC outputs (OUTA, OUTB) represent the data held in the two 8-bit
Low-Power Shutdown Mode
The MAX5102 features a shutdown mode that reduces current consumption to 1nA. A high voltage on the SHDN pin shuts down the DACs and the output amplifiers. In shutdown mode, the output amplifiers enter a high-impedance state. When bringing the device out of shutdown, allow 13s for the output to stabilize.
Table 1. MAX5102 Addressing Table (partial list)
WR H L L A0 X L H LATCH STATE Input data latched DAC A input latch transparent DAC B input latch transparent
Output Buffer Amplifiers
The DAC outputs are internally buffered by precision amplifiers with a typical slew rate of 0.6V/s. The typical settling time to 1/2LSB at the output is 6s when loaded with 10k in parallel with 100pF.
H = High state, L = Low state, X = Don't care
6
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+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
input latches. To avoid output glitches in the MAX5102, ensure that data is valid before WR goes low. When the device powers up (i.e., VDD ramps up), all latches are internally preset with code 00 hex. connect an external Schottky diode between REF and VDD to ensure compliance with the absolute maximum ratings. Do not apply signals to the digital inputs before the device is fully powered up.
MAX5102
Applications Information
External Reference
The reference source resistance must be considerably less than the reference input resistance. To keep within 1LSB error in an 8-bit system, RS must be less than R REF /256. Hence, maintain a value of R S < 1k to ensure 8-bit accuracy. If VREF is DC only, bypass REF to GND with a 0.1F capacitor. Values greater than this improve noise rejection.
Power-Supply Bypassing and Ground Management
Digital or AC transient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass VDD with a 0.1F capacitor, located as close to VDD and GND as possible. Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs.
Power Sequencing
The voltage applied to REF should not exceed VDD at any time. If proper power sequencing is not possible, TRANSISTOR COUNT: 6848
Chip Information
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7
+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5102
Package Information
TSSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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